Implement VirtDriver using opendc-simulator-compute module

This change adds an implementation of the VirtDriver interface that uses
the functionality provided by the opendc-simulator-compute module.

2 files changed, 133 insertions, 3 deletions

diff --git a/simulator/opendc-simulator/opendc-simulator-compute/src/test/kotlin/org/opendc/simulator/compute/SimHypervisorTest.kt b/simulator/opendc-simulator/opendc-simulator-compute/src/test/kotlin/org/opendc/simulator/compute/SimHypervisorTest.kt
new file mode 100644
index 00000000..b9cd1b06
--- /dev/null
+++ b/simulator/opendc-simulator/opendc-simulator-compute/src/test/kotlin/org/opendc/simulator/compute/SimHypervisorTest.kt
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2020 AtLarge Research
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+package org.opendc.simulator.compute
+
+import kotlinx.coroutines.ExperimentalCoroutinesApi
+import kotlinx.coroutines.launch
+import kotlinx.coroutines.test.TestCoroutineScope
+import kotlinx.coroutines.yield
+import org.junit.jupiter.api.Assertions
+import org.junit.jupiter.api.BeforeEach
+import org.junit.jupiter.api.Test
+import org.junit.jupiter.api.assertAll
+import org.opendc.simulator.compute.model.MemoryUnit
+import org.opendc.simulator.compute.model.ProcessingNode
+import org.opendc.simulator.compute.model.ProcessingUnit
+import org.opendc.simulator.compute.workload.SimTraceWorkload
+import org.opendc.simulator.utils.DelayControllerClockAdapter
+import java.time.Clock
+import java.util.*
+
+/**
+ * Test suite for the [SimHypervisor] class.
+ */
+@OptIn(ExperimentalCoroutinesApi::class)
+internal class SimHypervisorTest {
+    private lateinit var scope: TestCoroutineScope
+    private lateinit var clock: Clock
+    private lateinit var machineModel: SimMachineModel
+
+    @BeforeEach
+    fun setUp() {
+        scope = TestCoroutineScope()
+        clock = DelayControllerClockAdapter(scope)
+
+        val cpuNode = ProcessingNode("Intel", "Xeon", "amd64", 2)
+        machineModel = SimMachineModel(
+            cpus = List(cpuNode.coreCount) { ProcessingUnit(cpuNode, it, 3200.0) },
+            memory = List(4) { MemoryUnit("Crucial", "MTA18ASF4G72AZ-3G2B1", 3200.0, 32_000) }
+        )
+    }
+
+    /**
+     * Test overcommissioning of a hypervisor.
+     */
+    @Test
+    fun overcommission() {
+        val listener = object : SimHypervisor.Listener {
+            var totalRequestedBurst = 0L
+            var totalGrantedBurst = 0L
+            var totalOvercommissionedBurst = 0L
+
+            override fun onSliceFinish(
+                hypervisor: SimHypervisor,
+                requestedBurst: Long,
+                grantedBurst: Long,
+                overcommissionedBurst: Long,
+                interferedBurst: Long,
+                cpuUsage: Double,
+                cpuDemand: Double
+            ) {
+                totalRequestedBurst += requestedBurst
+                totalGrantedBurst += grantedBurst
+                totalOvercommissionedBurst += overcommissionedBurst
+            }
+        }
+
+        scope.launch {
+            val duration = 5 * 60L
+            val workloadA =
+                SimTraceWorkload(
+                    sequenceOf(
+                        SimTraceWorkload.Fragment(0, 28L * duration, duration * 1000, 28.0, 2),
+                        SimTraceWorkload.Fragment(0, 3500L * duration, duration * 1000, 3500.0, 2),
+                        SimTraceWorkload.Fragment(0, 0, duration * 1000, 0.0, 2),
+                        SimTraceWorkload.Fragment(0, 183L * duration, duration * 1000, 183.0, 2)
+                    ),
+                )
+            val workloadB =
+                SimTraceWorkload(
+                    sequenceOf(
+                        SimTraceWorkload.Fragment(0, 28L * duration, duration * 1000, 28.0, 2),
+                        SimTraceWorkload.Fragment(0, 3100L * duration, duration * 1000, 3100.0, 2),
+                        SimTraceWorkload.Fragment(0, 0, duration * 1000, 0.0, 2),
+                        SimTraceWorkload.Fragment(0, 73L * duration, duration * 1000, 73.0, 2)
+                    )
+                )
+
+            val machine = SimBareMetalMachine(scope, clock, machineModel)
+            val hypervisor = SimHypervisor(scope, clock, listener)
+
+            launch {
+                machine.run(hypervisor)
+            }
+
+            yield()
+            launch { hypervisor.createMachine(machineModel).run(workloadA) }
+            launch { hypervisor.createMachine(machineModel).run(workloadB) }
+        }
+
+        scope.advanceUntilIdle()
+
+        assertAll(
+            { Assertions.assertEquals(emptyList<Throwable>(), scope.uncaughtExceptions, "No errors") },
+            { Assertions.assertEquals(2073600, listener.totalRequestedBurst, "Requested Burst does not match") },
+            { Assertions.assertEquals(2013600, listener.totalGrantedBurst, "Granted Burst does not match") },
+            { Assertions.assertEquals(60000, listener.totalOvercommissionedBurst, "Overcommissioned Burst does not match") },
+            { Assertions.assertEquals(1200001, scope.currentTime) }
+        )
+    }
+}
diff --git a/simulator/opendc-simulator/opendc-simulator-compute/src/test/kotlin/org/opendc/simulator/compute/SimMachineTest.kt b/simulator/opendc-simulator/opendc-simulator-compute/src/test/kotlin/org/opendc/simulator/compute/SimMachineTest.kt
index f6fb8e04..332ca8e9 100644
--- a/simulator/opendc-simulator/opendc-simulator-compute/src/test/kotlin/org/opendc/simulator/compute/SimMachineTest.kt
+++ b/simulator/opendc-simulator/opendc-simulator-compute/src/test/kotlin/org/opendc/simulator/compute/SimMachineTest.kt
@@ -35,7 +35,7 @@ import org.opendc.simulator.compute.workload.SimFlopsWorkload
 import org.opendc.simulator.utils.DelayControllerClockAdapter
 
 /**
- * Test suite for the [SimMachine] class.
+ * Test suite for the [SimBareMetalMachine] class.
  */
 @OptIn(ExperimentalCoroutinesApi::class)
 class SimMachineTest {
@@ -55,7 +55,7 @@ class SimMachineTest {
     fun testFlopsWorkload() {
         val testScope = TestCoroutineScope()
         val clock = DelayControllerClockAdapter(testScope)
-        val machine = SimMachine(testScope, clock, machineModel)
+        val machine = SimBareMetalMachine(testScope, clock, machineModel)
 
         testScope.runBlockingTest {
             machine.run(SimFlopsWorkload(2_000, 2, utilization = 1.0))
@@ -69,7 +69,7 @@ class SimMachineTest {
     fun testUsage() {
         val testScope = TestCoroutineScope()
         val clock = DelayControllerClockAdapter(testScope)
-        val machine = SimMachine(testScope, clock, machineModel)
+        val machine = SimBareMetalMachine(testScope, clock, machineModel)
 
         testScope.runBlockingTest {
             machine.run(SimFlopsWorkload(2_000, 2, utilization = 1.0))