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authorFabian Mastenbroek <mail.fabianm@gmail.com>2021-03-17 16:51:38 +0100
committerGitHub <noreply@github.com>2021-03-17 16:51:38 +0100
commit054a3d376b8b31ba98f91e7b34c6e0ca717def18 (patch)
treeee739cf4092a2b807e0043bed7cae72cff7b6bac /simulator/opendc-compute
parentdf2f52780c08c5d108741d3746eaf03222c64841 (diff)
parentbb3b8e207a08edff81b8c2fe30b476c94bfea086 (diff)
Add uniform resource consumption model (v1)
This is the first in the series of pull requests to add a uniform resource consumption model to OpenDC. This pull request introduces the `opendc-simulator-resources` module which introduces the primitives with which we can model resource consumption of CPUs, disks and network: * `SimResourceProvider` represents a provider of some generic resource `R`, which may be consumed via `consume(SimResourceConsumer<R>)` * `SimResourceConsumer` represents a resource consumers and characterizes how the resource is being consumed. * `SimResourceSwitch` is a generic scheduler for sharing the capacity of multiple resources across multiple consumers. - `SimResourceSwitchExclusive`: A space-shared switch - each consumer is allocated a single resource exclusively. - `SimResourceSwitchMinMax`: A time-shared switch - each consumer gets a fair share of the resource capacity. * `SimResourceForwarder` converts a consumer in a provider. **Breaking Changes** * `ProcessingUnit` and `MemoryUnit` renamed to `SimProcessingUnit` and `SimMemoryUnit` respectively. * `TimerScheduler` accepts a `CoroutineContext` as opposed to a `CoroutineScope`.
Diffstat (limited to 'simulator/opendc-compute')
-rw-r--r--simulator/opendc-compute/opendc-compute-service/src/main/kotlin/org/opendc/compute/service/internal/ComputeServiceImpl.kt2
-rw-r--r--simulator/opendc-compute/opendc-compute-simulator/src/main/kotlin/org/opendc/compute/simulator/SimHost.kt7
-rw-r--r--simulator/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt16
3 files changed, 13 insertions, 12 deletions
diff --git a/simulator/opendc-compute/opendc-compute-service/src/main/kotlin/org/opendc/compute/service/internal/ComputeServiceImpl.kt b/simulator/opendc-compute/opendc-compute-service/src/main/kotlin/org/opendc/compute/service/internal/ComputeServiceImpl.kt
index 2c38f7cb..aa7e0aa1 100644
--- a/simulator/opendc-compute/opendc-compute-service/src/main/kotlin/org/opendc/compute/service/internal/ComputeServiceImpl.kt
+++ b/simulator/opendc-compute/opendc-compute-service/src/main/kotlin/org/opendc/compute/service/internal/ComputeServiceImpl.kt
@@ -125,7 +125,7 @@ public class ComputeServiceImpl(
/**
* The [TimerScheduler] to use for scheduling the scheduler cycles.
*/
- private var scheduler: TimerScheduler<Unit> = TimerScheduler(scope, clock)
+ private var scheduler: TimerScheduler<Unit> = TimerScheduler(scope.coroutineContext, clock)
override val hosts: Set<Host>
get() = hostToView.keys
diff --git a/simulator/opendc-compute/opendc-compute-simulator/src/main/kotlin/org/opendc/compute/simulator/SimHost.kt b/simulator/opendc-compute/opendc-compute-simulator/src/main/kotlin/org/opendc/compute/simulator/SimHost.kt
index 19fa3e97..9cc1bf54 100644
--- a/simulator/opendc-compute/opendc-compute-simulator/src/main/kotlin/org/opendc/compute/simulator/SimHost.kt
+++ b/simulator/opendc-compute/opendc-compute-simulator/src/main/kotlin/org/opendc/compute/simulator/SimHost.kt
@@ -35,7 +35,7 @@ import org.opendc.compute.simulator.power.models.ConstantPowerModel
import org.opendc.simulator.compute.*
import org.opendc.simulator.compute.interference.IMAGE_PERF_INTERFERENCE_MODEL
import org.opendc.simulator.compute.interference.PerformanceInterferenceModel
-import org.opendc.simulator.compute.model.MemoryUnit
+import org.opendc.simulator.compute.model.SimMemoryUnit
import org.opendc.simulator.failures.FailureDomain
import org.opendc.utils.flow.EventFlow
import java.time.Clock
@@ -84,7 +84,7 @@ public class SimHost(
/**
* The machine to run on.
*/
- public val machine: SimBareMetalMachine = SimBareMetalMachine(scope, clock, model)
+ public val machine: SimBareMetalMachine = SimBareMetalMachine(context, clock, model)
/**
* The hypervisor to run multiple workloads.
@@ -206,6 +206,7 @@ public class SimHost(
override fun close() {
scope.cancel()
+ machine.close()
_state = HostState.DOWN
}
@@ -216,7 +217,7 @@ public class SimHost(
val originalCpu = machine.model.cpus[0]
val processingNode = originalCpu.node.copy(coreCount = cpuCount)
val processingUnits = (0 until cpuCount).map { originalCpu.copy(id = it, node = processingNode) }
- val memoryUnits = listOf(MemoryUnit("Generic", "Generic", 3200.0, memorySize))
+ val memoryUnits = listOf(SimMemoryUnit("Generic", "Generic", 3200.0, memorySize))
return SimMachineModel(processingUnits, memoryUnits)
}
diff --git a/simulator/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt b/simulator/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt
index e1a1d87e..6929b06c 100644
--- a/simulator/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt
+++ b/simulator/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt
@@ -40,9 +40,9 @@ import org.opendc.compute.api.ServerWatcher
import org.opendc.compute.service.driver.HostEvent
import org.opendc.simulator.compute.SimFairShareHypervisorProvider
import org.opendc.simulator.compute.SimMachineModel
-import org.opendc.simulator.compute.model.MemoryUnit
-import org.opendc.simulator.compute.model.ProcessingNode
-import org.opendc.simulator.compute.model.ProcessingUnit
+import org.opendc.simulator.compute.model.SimMemoryUnit
+import org.opendc.simulator.compute.model.SimProcessingNode
+import org.opendc.simulator.compute.model.SimProcessingUnit
import org.opendc.simulator.compute.workload.SimTraceWorkload
import org.opendc.simulator.utils.DelayControllerClockAdapter
import java.time.Clock
@@ -62,11 +62,11 @@ internal class SimHostTest {
scope = TestCoroutineScope()
clock = DelayControllerClockAdapter(scope)
- val cpuNode = ProcessingNode("Intel", "Xeon", "amd64", 2)
+ val cpuNode = SimProcessingNode("Intel", "Xeon", "amd64", 2)
machineModel = SimMachineModel(
- cpus = List(cpuNode.coreCount) { ProcessingUnit(cpuNode, it, 3200.0) },
- memory = List(4) { MemoryUnit("Crucial", "MTA18ASF4G72AZ-3G2B1", 3200.0, 32_000) }
+ cpus = List(cpuNode.coreCount) { SimProcessingUnit(cpuNode, it, 3200.0) },
+ memory = List(4) { SimMemoryUnit("Crucial", "MTA18ASF4G72AZ-3G2B1", 3200.0, 32_000) }
)
}
@@ -136,8 +136,8 @@ internal class SimHostTest {
assertAll(
{ assertEquals(emptyList<Throwable>(), scope.uncaughtExceptions, "No errors") },
- { assertEquals(4197600, requestedWork, "Requested work does not match") },
- { assertEquals(3057600, grantedWork, "Granted work does not match") },
+ { assertEquals(4273200, requestedWork, "Requested work does not match") },
+ { assertEquals(3133200, grantedWork, "Granted work does not match") },
{ assertEquals(1140000, overcommittedWork, "Overcommitted work does not match") },
{ assertEquals(1200006, scope.currentTime) }
)