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authorFabian Mastenbroek <mail.fabianm@gmail.com>2020-02-28 15:59:14 +0100
committerFabian Mastenbroek <mail.fabianm@gmail.com>2020-02-28 15:59:14 +0100
commitf13cda61c142ff3d1a2e75de2b05667bdb3ab3ae (patch)
tree90b977f7a9c3584c24787d0769ff6b5d9ef0323a /opendc/opendc-format/src
parentac6e6f7c611fa7d10fff5467c4a61af932e4c171 (diff)
refactor: Create distinction between CPU node and core
This change updates the terminology in the `opendc-compute` module to make a distinction between CPU node and CPU core, where we primarly work with CPU cores. However, if needed, we also provide information for the different CPU nodes.
Diffstat (limited to 'opendc/opendc-format/src')
-rw-r--r--opendc/opendc-format/src/main/kotlin/com/atlarge/opendc/format/environment/sc18/Sc18EnvironmentReader.kt13
-rw-r--r--opendc/opendc-format/src/main/kotlin/com/atlarge/opendc/format/environment/sc20/Sc20EnvironmentReader.kt13
2 files changed, 20 insertions, 6 deletions
diff --git a/opendc/opendc-format/src/main/kotlin/com/atlarge/opendc/format/environment/sc18/Sc18EnvironmentReader.kt b/opendc/opendc-format/src/main/kotlin/com/atlarge/opendc/format/environment/sc18/Sc18EnvironmentReader.kt
index 8898ddc7..942a8c72 100644
--- a/opendc/opendc-format/src/main/kotlin/com/atlarge/opendc/format/environment/sc18/Sc18EnvironmentReader.kt
+++ b/opendc/opendc-format/src/main/kotlin/com/atlarge/opendc/format/environment/sc18/Sc18EnvironmentReader.kt
@@ -27,6 +27,7 @@ package com.atlarge.opendc.format.environment.sc18
import com.atlarge.odcsim.Domain
import com.atlarge.opendc.compute.core.ProcessingUnit
import com.atlarge.opendc.compute.core.MemoryUnit
+import com.atlarge.opendc.compute.core.ProcessingNode
import com.atlarge.opendc.compute.metal.driver.SimpleBareMetalDriver
import com.atlarge.opendc.compute.metal.service.ProvisioningService
import com.atlarge.opendc.compute.metal.service.SimpleProvisioningService
@@ -63,10 +64,16 @@ class Sc18EnvironmentReader(input: InputStream, mapper: ObjectMapper = jacksonOb
when (roomObject) {
is RoomObject.Rack -> {
roomObject.machines.map { machine ->
- val cores = machine.cpus.map { id ->
+ val cores = machine.cpus.flatMap { id ->
when (id) {
- 1 -> ProcessingUnit("Intel", "Core(TM) i7-6920HQ", "amd64", 4100.0, 4)
- 2 -> ProcessingUnit("Intel", "Core(TM) I7-6920HQ", "amd64", 3500.0, 2)
+ 1 -> {
+ val node = ProcessingNode("Intel", "Core(TM) i7-6920HQ", "amd64", 4)
+ List(node.coreCount) { ProcessingUnit(node, it, 4100.0) }
+ }
+ 2 -> {
+ val node = ProcessingNode("Intel", "Core(TM) i7-6920HQ", "amd64", 2)
+ List(node.coreCount) { ProcessingUnit(node, it, 3500.0) }
+ }
else -> throw IllegalArgumentException("The cpu id $id is not recognized")
}
}
diff --git a/opendc/opendc-format/src/main/kotlin/com/atlarge/opendc/format/environment/sc20/Sc20EnvironmentReader.kt b/opendc/opendc-format/src/main/kotlin/com/atlarge/opendc/format/environment/sc20/Sc20EnvironmentReader.kt
index fecba302..b33a5e93 100644
--- a/opendc/opendc-format/src/main/kotlin/com/atlarge/opendc/format/environment/sc20/Sc20EnvironmentReader.kt
+++ b/opendc/opendc-format/src/main/kotlin/com/atlarge/opendc/format/environment/sc20/Sc20EnvironmentReader.kt
@@ -26,6 +26,7 @@ package com.atlarge.opendc.format.environment.sc20
import com.atlarge.odcsim.Domain
import com.atlarge.opendc.compute.core.MemoryUnit
+import com.atlarge.opendc.compute.core.ProcessingNode
import com.atlarge.opendc.compute.core.ProcessingUnit
import com.atlarge.opendc.compute.metal.driver.SimpleBareMetalDriver
import com.atlarge.opendc.compute.metal.service.ProvisioningService
@@ -60,10 +61,16 @@ class Sc20EnvironmentReader(input: InputStream, mapper: ObjectMapper = jacksonOb
when (roomObject) {
is RoomObject.Rack -> {
roomObject.machines.map { machine ->
- val cores = machine.cpus.map { id ->
+ val cores = machine.cpus.flatMap { id ->
when (id) {
- 1 -> ProcessingUnit("Intel", "Core(TM) i7-6920HQ", "amd64", 4100.0, 4)
- 2 -> ProcessingUnit("Intel", "Core(TM) I7-6920HQ", "amd64", 3500.0, 2)
+ 1 -> {
+ val node = ProcessingNode("Intel", "Core(TM) i7-6920HQ", "amd64", 4)
+ List(node.coreCount) { ProcessingUnit(node, it, 4100.0) }
+ }
+ 2 -> {
+ val node = ProcessingNode("Intel", "Core(TM) i7-6920HQ", "amd64", 2)
+ List(node.coreCount) { ProcessingUnit(node, it, 3500.0) }
+ }
else -> throw IllegalArgumentException("The cpu id $id is not recognized")
}
}