diff options
| author | Fabian Mastenbroek <mail.fabianm@gmail.com> | 2022-09-22 14:45:12 +0200 |
|---|---|---|
| committer | Fabian Mastenbroek <mail.fabianm@gmail.com> | 2022-09-22 14:50:00 +0200 |
| commit | 17fa7619f1d7e96680e018d3f12f333fb75cdac1 (patch) | |
| tree | 5acabfb33d5fa2c624926df91264e460d2afb761 /opendc-compute/opendc-compute-simulator/src/test/kotlin/org | |
| parent | 8b6c15193281171bcb2e111f339ffb8da385332b (diff) | |
refactor(sim/compute): Make interference domain independent of profile
This change updates the virtual machine performance interference model
so that the interference domain can be constructed independently of the
interference profile. As a consequence, the construction of the topology
now does not depend anymore on the interference profile.
Diffstat (limited to 'opendc-compute/opendc-compute-simulator/src/test/kotlin/org')
| -rw-r--r-- | opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt b/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt index 06500a06..879f15b2 100644 --- a/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt +++ b/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt @@ -71,7 +71,7 @@ internal class SimHostTest { val duration = 5 * 60L val engine = FlowEngine(coroutineContext, clock) val machine = SimBareMetalMachine(engine, machineModel, SimplePowerDriver(ConstantPowerModel(0.0))) - val hypervisor = SimFairShareHypervisor(engine, null, SplittableRandom(1)) + val hypervisor = SimFairShareHypervisor(engine, SplittableRandom(1), null) val host = SimHost( uid = UUID.randomUUID(), name = "test", @@ -155,7 +155,7 @@ internal class SimHostTest { val duration = 5 * 60L val engine = FlowEngine(coroutineContext, clock) val machine = SimBareMetalMachine(engine, machineModel, SimplePowerDriver(ConstantPowerModel(0.0))) - val hypervisor = SimFairShareHypervisor(engine, null, SplittableRandom(1)) + val hypervisor = SimFairShareHypervisor(engine, SplittableRandom(1), null) val host = SimHost( uid = UUID.randomUUID(), name = "test", |