feat: new figure in slide 2; backup commit for previous figures

12 files changed, 56 insertions, 64 deletions

diff --git a/build/main.aux b/build/main.aux
index 38b0255..033f445 100644
--- a/build/main.aux
+++ b/build/main.aux
@@ -7,7 +7,6 @@
 \citation{DBLP:conf/date/MilojicicFDR21}
 \citation{DBLP:image/48Microprocessor/Rupp}
 \citation{DBLP:journals/computer/AthavaleBBMMPS24}
-\citation{Wikipedia:AdaLovelaceArchi}
 \citation{DBLP:journals/computer/AthavaleBBMMPS24}
 \@writefile{nav}{\headcommand {\slideentry {0}{0}{2}{2/2}{}{0}}}
 \@writefile{nav}{\headcommand {\beamer@framepages {2}{2}}}
@@ -50,8 +49,7 @@
 \bibcite{DBLP:conf/acsos/TalluriOVTI21}{\hyperlink {beamerbibDBLP:conf/acsos/TalluriOVTI21}{12}}
 \bibcite{DBLP:conf/cirp/TAO2018169}{\hyperlink {beamerbibDBLP:conf/cirp/TAO2018169}{13}}
 \bibcite{DBLP:conf/sensys/WangZD0TCWZ20}{\hyperlink {beamerbibDBLP:conf/sensys/WangZD0TCWZ20}{14}}
-\bibcite{Wikipedia:AdaLovelaceArchi}{\hyperlink {beamerbibWikipedia:AdaLovelaceArchi}{15}}
-\bibcite{DBLP:conf/noms/ZhangZLZWC22}{\hyperlink {beamerbibDBLP:conf/noms/ZhangZLZWC22}{16}}
+\bibcite{DBLP:conf/noms/ZhangZLZWC22}{\hyperlink {beamerbibDBLP:conf/noms/ZhangZLZWC22}{15}}
 \@writefile{nav}{\headcommand {\slideentry {0}{0}{10}{10/10}{}{0}}}
 \@writefile{nav}{\headcommand {\beamer@framepages {10}{10}}}
 \@writefile{nav}{\headcommand {\slideentry {0}{0}{10}{10/11}{}{0}}}
diff --git a/build/main.bbl b/build/main.bbl
index 91827b2..1bc85d5 100644
--- a/build/main.bbl
+++ b/build/main.bbl
@@ -95,12 +95,6 @@ Ruihang Wang, Xin Zhou, Linsen Dong, Yonggang Wen, Rui Tan, Li~Chen, Guan Wang,
 \newblock In {\em BuildSys '20: The 7th {ACM} International Conference on Systems for Energy-Efficient Buildings, Cities, and Transportation, Virtual Event, Japan, November 18-20, 2020}, pages 200--209. {ACM}, 2020.
 \newblock \ifshowURL {\showURL \path|https://doi.org/10.1145/3408308.3427982|}\fi.
 
-\bibitem{Wikipedia:AdaLovelaceArchi}
-{Wikipedia contributors}.
-\newblock Ada lovelace (microarchitecture) --- {Wikipedia}{,} the free encyclopedia.
-\newblock \url{ https://en.wikipedia.org/w/index.php?title=Ada_Lovelace_(microarchitecture)&oldid=1353150869 }, 2026.
-\newblock [Online; accessed 10-June-2026].
-
 \bibitem{DBLP:conf/noms/ZhangZLZWC22}
 Ziting Zhang, Yu~Zeng, Haoran Liu, Chaoyue Zhao, Feng Wang, and Yunqing Chen.
 \newblock Smart {DC:} an {AI} and digital twin-based energy-saving solution for data centers.
diff --git a/build/main.blg b/build/main.blg
index f142293..cc3d2af 100644
--- a/build/main.blg
+++ b/build/main.blg
@@ -6,45 +6,45 @@ Database file #1: main.bib
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 --line 676 of file main.bib
 Warning--empty booktitle in DBLP:usdoe/report/AP26894
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-and the built_in function-call counts, 9873 in all, are:
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-> -- 560
+            692 strings with 11146 characters,
+and the built_in function-call counts, 9624 in all, are:
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 < -- 9
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-- -- 202
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++ -- 216
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 missing$ -- 13
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diff --git a/build/main.fdb_latexmk b/build/main.fdb_latexmk
index 4c000d2..714cbe1 100644
--- a/build/main.fdb_latexmk
+++ b/build/main.fdb_latexmk
@@ -1,13 +1,13 @@
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   "build/main.bbl"
   "build/main.blg"
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@@ -287,7 +287,7 @@
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diff --git a/build/main.fls b/build/main.fls
index ac0d19e..9e878a3 100644
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@@ -550,12 +550,12 @@ INPUT ./images/nvidiagpu.png
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diff --git a/build/main.log b/build/main.log
index 00e80fc..65ea61e 100644
--- a/build/main.log
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@@ -1,4 +1,4 @@
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diff --git a/build/main.pdf b/build/main.pdf
index 113df39..af3b648 100644
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diff --git a/build/main.synctex.gz b/build/main.synctex.gz
index 04cfb15..8393fd6 100644
--- a/build/main.synctex.gz
+++ b/build/main.synctex.gz
diff --git a/images/datacenter_complexity.pdf b/images/datacenter_complexity.pdf
new file mode 100644
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diff --git a/images/fig1.psd b/images/fig1.psd
new file mode 100644
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diff --git a/indent.log b/indent.log
index 53edf62..c66a685 100644
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diff --git a/main.tex b/main.tex
index 133df11..018294b 100644
--- a/main.tex
+++ b/main.tex
@@ -16,8 +16,8 @@
 			\includegraphics[width=0.7\linewidth]{images/nvidiagpu.png}
 		\end{center}
 		\vspace{-0.2cm}
-		\textbf{Figure 1.1:} Nvidia Ada Lovelace AD102 Architecture, present in all GPUs from 2022 onwards~\cite{Wikipedia:AdaLovelaceArchi}.
-		Source: official renderings by Nvidia.
+		%\textbf{Figure 1.1:} Nvidia Ada Lovelace AD102 Architecture, present in all GPUs from 2022 onwards~\cite{Wikipedia:AdaLovelaceArchi}.
+		%Source: official renderings by Nvidia.
 		%\textbf{Figure 1.1:} 48 years of microprocessor trend data. Legend: \textcolor{Orange}{$\bigblacktriangleup$ Transistors (thousands)}, \textcolor{Blue}{$\lgblkcircle$ Single Thread Performance (SpecINT $\times 10^3$)}, \textcolor{Green}{$\lgblksquare$ Frequency (MHz)}, \textcolor{Maroon}{$\bigblacktriangledown$ Typical Power (Watts)}, $\mdlgblkdiamond$ Number of Logical Cores~\cite{DBLP:image/48Microprocessor/Rupp}.
 	\end{minipage}
 	\hspace{0.5cm}