From 3718c385f84b463ac799080bb5603e0011adcd7d Mon Sep 17 00:00:00 2001
From: Fabian Mastenbroek <mail.fabianm@gmail.com>
Date: Mon, 22 Mar 2021 16:45:13 +0100
Subject: simulator: Remove generic resource constraint from resource model

This change removes the generic resource constraint (e.g., SimResource)
and replaces it by a simple capacity property. In the future, users
should handle the resource properties on a higher level.

This change simplifies compositions of consumers and providers by not
requiring a translation from resource to capacity.
---
 .../main/kotlin/org/opendc/compute/simulator/SimHost.kt  |  4 ++--
 .../kotlin/org/opendc/compute/simulator/SimHostTest.kt   | 16 ++++++++--------
 2 files changed, 10 insertions(+), 10 deletions(-)

(limited to 'simulator/opendc-compute')

diff --git a/simulator/opendc-compute/opendc-compute-simulator/src/main/kotlin/org/opendc/compute/simulator/SimHost.kt b/simulator/opendc-compute/opendc-compute-simulator/src/main/kotlin/org/opendc/compute/simulator/SimHost.kt
index 6e9b8151..694676bc 100644
--- a/simulator/opendc-compute/opendc-compute-simulator/src/main/kotlin/org/opendc/compute/simulator/SimHost.kt
+++ b/simulator/opendc-compute/opendc-compute-simulator/src/main/kotlin/org/opendc/compute/simulator/SimHost.kt
@@ -35,7 +35,7 @@ import org.opendc.compute.simulator.power.models.ConstantPowerModel
 import org.opendc.simulator.compute.*
 import org.opendc.simulator.compute.interference.IMAGE_PERF_INTERFERENCE_MODEL
 import org.opendc.simulator.compute.interference.PerformanceInterferenceModel
-import org.opendc.simulator.compute.model.SimMemoryUnit
+import org.opendc.simulator.compute.model.MemoryUnit
 import org.opendc.simulator.failures.FailureDomain
 import org.opendc.utils.flow.EventFlow
 import java.time.Clock
@@ -217,7 +217,7 @@ public class SimHost(
         val originalCpu = machine.model.cpus[0]
         val processingNode = originalCpu.node.copy(coreCount = cpuCount)
         val processingUnits = (0 until cpuCount).map { originalCpu.copy(id = it, node = processingNode) }
-        val memoryUnits = listOf(SimMemoryUnit("Generic", "Generic", 3200.0, memorySize))
+        val memoryUnits = listOf(MemoryUnit("Generic", "Generic", 3200.0, memorySize))
 
         return SimMachineModel(processingUnits, memoryUnits)
     }
diff --git a/simulator/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt b/simulator/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt
index d7a3b744..e311cd21 100644
--- a/simulator/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt
+++ b/simulator/opendc-compute/opendc-compute-simulator/src/test/kotlin/org/opendc/compute/simulator/SimHostTest.kt
@@ -40,9 +40,9 @@ import org.opendc.compute.api.ServerWatcher
 import org.opendc.compute.service.driver.HostEvent
 import org.opendc.simulator.compute.SimFairShareHypervisorProvider
 import org.opendc.simulator.compute.SimMachineModel
-import org.opendc.simulator.compute.model.SimMemoryUnit
-import org.opendc.simulator.compute.model.SimProcessingNode
-import org.opendc.simulator.compute.model.SimProcessingUnit
+import org.opendc.simulator.compute.model.MemoryUnit
+import org.opendc.simulator.compute.model.ProcessingNode
+import org.opendc.simulator.compute.model.ProcessingUnit
 import org.opendc.simulator.compute.workload.SimTraceWorkload
 import org.opendc.simulator.utils.DelayControllerClockAdapter
 import java.time.Clock
@@ -62,11 +62,11 @@ internal class SimHostTest {
         scope = TestCoroutineScope()
         clock = DelayControllerClockAdapter(scope)
 
-        val cpuNode = SimProcessingNode("Intel", "Xeon", "amd64", 2)
+        val cpuNode = ProcessingNode("Intel", "Xeon", "amd64", 2)
 
         machineModel = SimMachineModel(
-            cpus = List(cpuNode.coreCount) { SimProcessingUnit(cpuNode, it, 3200.0) },
-            memory = List(4) { SimMemoryUnit("Crucial", "MTA18ASF4G72AZ-3G2B1", 3200.0, 32_000) }
+            cpus = List(cpuNode.coreCount) { ProcessingUnit(cpuNode, it, 3200.0) },
+            memory = List(4) { MemoryUnit("Crucial", "MTA18ASF4G72AZ-3G2B1", 3200.0, 32_000) }
         )
     }
 
@@ -136,8 +136,8 @@ internal class SimHostTest {
 
         assertAll(
             { assertEquals(emptyList<Throwable>(), scope.uncaughtExceptions, "No errors") },
-            { assertEquals(4281600, requestedWork, "Requested work does not match") },
-            { assertEquals(2241600, grantedWork, "Granted work does not match") },
+            { assertEquals(4197600, requestedWork, "Requested work does not match") },
+            { assertEquals(2157600, grantedWork, "Granted work does not match") },
             { assertEquals(2040000, overcommittedWork, "Overcommitted work does not match") },
             { assertEquals(1200006, scope.currentTime) }
         )
-- 
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