From 311c1fc5dfc5ec5b626fea61e5f098191f865ff2 Mon Sep 17 00:00:00 2001
From: mjkwiatkowski <mati.rewa@gmail.com>
Date: Tue, 9 Jun 2026 17:55:02 +0200
Subject: initial commit

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 main.tex | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 67 insertions(+), 8 deletions(-)

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diff --git a/main.tex b/main.tex
index a897b0e..9238735 100644
--- a/main.tex
+++ b/main.tex
@@ -1,14 +1,73 @@
-\documentclass{article}
-\usepackage{graphicx} % Required for inserting images
+\documentclass[12pt, handout]{beamer}
+\input{style/style.tex}
+\begin{document}
 
-\title{VU BSc Defense Slides Mateusz Kwiatkowski}
-\author{Mateusz Kwiatkowski}
-\date{June 2026}
+\frame{\titlepage}
 
-\begin{document}
+\begin{frame}\frametitle{Motivation}
+	\begin{tcolorbox}[title=Context]
+		Heterogeneous datacenter architectures are common~\cite{DBLP:conf/date/MilojicicFDR21} due to the end of Dennard's scaling.
+		Nowadays, computational needs of AI drive managers to diversify datacenters even more~\cite{DBLP:journals/computer/AthavaleBBMMPS24}.
+		In result datacenters become extremely complex and hard to operate.
+	\end{tcolorbox}
+	\begin{minipage}[t]{0.45\linewidth}
+		\tiny
+		{\centering
+			\includegraphics[width=1.05\linewidth]{images/48-years-processor-trend-2.pdf}
+		}
+		\textbf{Figure 1.1:} 48 years of microprocessor trend data. Legend: \textcolor{Orange}{$\bigblacktriangleup$ Transistors (thousands)}, \textcolor{Blue}{$\lgblkcircle$ Single Thread Performance (SpecINT $\times 10^3$)}, \textcolor{Green}{$\lgblksquare$ Frequency (MHz)}, \textcolor{Maroon}{$\bigblacktriangledown$ Typical Power (Watts)}, $\mdlgblkdiamond$ Number of Logical Cores~\cite{DBLP:image/48Microprocessor/Rupp}.
+	\end{minipage}
+	\hspace{0.5cm}
+	\begin{minipage}[t]{0.45\linewidth}
+		{\centering
+			\includegraphics[width=1.1\linewidth]{images/AthavaleBBMMPS24_cropped.pdf}
+		}
+		\tiny
+		\textbf{Figure 1.2:} Explosive growth in AI computational requirements drives datacenter upgrades (source: NVIDIA Analysis: reproduction with NVIDIA permission by~\cite{DBLP:journals/computer/AthavaleBBMMPS24}).
+	\end{minipage}
+\end{frame}
+
+\begin{frame}\frametitle{Background}
+\end{frame}
+
+
+\begin{frame}\frametitle{Research Questions}
+	\begin{tcolorbox}[title=Main Research Question, colbacktitle=red!70!black,colback=red!20!white]
+		How to enable predictive analytics for datacenters through digital twinning?
+	\end{tcolorbox}
+
+	\begin{tcolorbox}[title=Research Question 1]
+		How to asses the current state-of-the-art of digital twinning for datacenters?
+	\end{tcolorbox}
+
+	\begin{tcolorbox}[title=Research Question 2]
+		How to design a datacenter digital twin reference architecture using discrete-event simulation and predictive data analytics?
+	\end{tcolorbox}
+
+	\begin{tcolorbox}[title=Research Question 3]
+		How to evaluate and validate a datacenter digital twin architecture in relation to system requirements?
+	\end{tcolorbox}
+\end{frame}
+
+
+\begin{frame}\frametitle{System model}
+\end{frame}
+
+
+\begin{frame}\frametitle{Reference Architecture}
+\end{frame}
+
+
+\begin{frame}\frametitle{Results}
+\end{frame}
 
-\maketitle
+\begin{frame}\frametitle{References}
+	\tiny
+	\bibliographystyle{is-plain}
+	\bibliography{main.bib}
+\end{frame}
 
-\section{Introduction}
 
+\begin{frame}\frametitle{Extra slides}
+\end{frame}
 \end{document}
-- 
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